One of the leading semiconductor products at the present time is a combination lateral and vertical field-effect-transistors (FET), which can be used in devices such as MESFETs, HFETs, etc.. These devices are especially useful in high voltage applications because they incorporate a vertical drift region formed in a relatively thick and low doped layer of material, generally including the substrate. However, to increase their utility or versatility, the FET should have low interelectrode capacitance, low ON-resistance, good switching characteristics (e.g. switching times, etc.), low leakage currents, high channel density, etc.
A MESFET with a buried shielding region is disclosed in a U.S. Pat. No. 5.077,589, entitled "MESFET Structure Having A Shielding Region", issued Dec. 31, 1991. The shielding region in the disclosed structure is a p-type doped region in an n-type transistor. Thus, p-type layers and p-type ohmic contacts are required during fabrication. Another device with a doped buried semiconductor region is disclosed in a copending application entitled "Lateral Gate, Vertical Drift Region Transistor", Ser. No. 08/681,684, filed 29 Jul. 1996 and assigned to the same assignee. In this device the buried region is also a semiconductor material doped opposite to the transistor. Because of the conductive buried layers in these types of devices, they have a relatively high source-drain and source channel capacitance which reduces the speed and degrades the frequency performance.
Accordingly, it would be highly advantageous to have a manufacturable FET with low internal capacitance, low ON-resistance, good switching characteristics (e.g. switching times, etc.), low leakage currents, high current density, etc.
It is a purpose of the present invention to provide a new and improved FET with low interelectrode capacitance.
It is another purpose of the present invention to provide a new and improved FET with low interelectrode capacitance which is relatively simple and inexpensive to manufacture because of reduced fabrication steps.
It is a further purpose of the present invention to provide a new and improved FET which can be fabricated in a variety of material systems and structures, including GaAs, GaN, and SiC, and MESFETs, HFETs, etc.